With recent advancement of semiconductor integrated circuitry (IC) technologies, electronic devices and/or products have been able to achieve lower power consumption and higher performance provided by the various integrated circuits that the electronic devices and/or products are made from. Generally, power consumption and performance of the various integrated circuits stem from/or are dependent upon capacitance, resistance, and leakage current of the components (electrical junctions, wires, dielectrics, etc) that the integrated circuits may contain, and operational current of the various transistors such as field-effect transistors (FETs) that the integrated circuits may include as well.
With shrinking dimensions of various integrated circuit components, transistors such as FETs have experienced dramatic improved performance over time. This improvement has been largely attributed to the reduced dimensions of components used therein, which generally translate into reduced capacitance and increased current for the transistors. Nevertheless, performance improvement brought up by this type of “classic” scaling, in device dimensions, has recently met obstacles and even been challenged, when the scaling goes beyond a certain point, by an increased leakage current and variability that are inevitably associated with this continued reduction in device dimensions.
So far, substantial efforts have been devoted to modify existing properties of transistors such FETs in order to improve power consumption and performance of the integrated circuit built from such transistors. As is generally known in the art, an FET usually contains various components including, for example, a deep diffusion region of source/drain and a shallower extension region that links a gate of the FET to the deep diffusion region of source/drain. In order to control and/or define a threshold voltage of the FET and possibly minimize leakage between source, drain and their extension regions, the FET usually contains a well and halo implant of opposite polarity near the deep diffusion and extension regions.
Furthermore, for example, in high performance logic integrated circuits, the above components of a FET are generally made or formed to be symmetric with respect to the gate of the FET. More specifically, the source-side structure may be made identical to the drain-side structure, that is, depth, dopant type, lateral diffusion extent of deep diffusion, extension, and halo implant may all intend to be made identical or at least substantially identical. Source and drain of a FET may only be distinguished by their electrical connectivity during usage. For example, in an n-type dopant doped FET (NFET), the drain may be a higher potential terminal, and in a p-type dopant doped FET (PFET) the drain may be a lower potential terminal, between a source terminal and a drain terminal of the FET.
It has been demonstrated that a regular FET with structural modification made independently to each side of the FET, in other words, an asymmetric FET structure may achieve better performance than a symmetric structure implementation of the FET in certain aspect. For example, it has been demonstrated that performance of an FET may be improved through reduction in resistance on the source side, with the use of higher source extension dosage, and through reduction in capacitance on the drain side, with the use of lower halo dosage or halo implant. In view of the potential benefits, different low cost manufacturing methods and/or approach of creating asymmetric FET structure have been explored.
So far, several methods have been proposed for creating asymmetric FET structures which include, for example, a method that uses a patterned photoresist to define regions that do not receive ion implants from regions, defined by openings in the patterned photoresist, that need to receive ion implants. For example, the source of a FET transistor may be unblocked for ion implant by an opening in a photoresist layer while the drain of the FET transistor will be blocked or covered by the photoresist layer. Further for example, a method is proposed wherein both the angle of implantation and the openings of photoresist need to be controlled carefully. By this method, a photoresist edge may block the implant into a nearby transistor by shadowing the angled implant even though the photoresist is open over the transistor that is to be blocked from implant. However, this method may not be able to accommodate creating FETs with relatively small geometry due to the difficulty in placing an edge of a photoresist over the FETs, which require the photoresist to block on one side and open on the other side of the FETs. As a result, a large variation in photoresist edge placement may occur which shrinks the manufacturing tolerance in the shadowing of the FETs during ion implantation.
The difficulties in creating asymmetry FET devices are expected to worsen even more with the transistors of shrinking dimension becoming to have even smaller geometries and the distance between them becoming even closer, as being generally predicated by the continued scaling in semiconductor technology. In particular, the technique and/or method currently proposed will encounter unavoidable difficulties in opening small areas of photoresist, with photoresist bridging, or scumming, onto adjacent transistor gates. Regions that are required to be opened in the photoresist exposure and development will be increasingly difficult to open when spacing between photoresist edge and FET gate become smaller. In such bridged regions, an implant will be fully or partially blocked while the intended action is not to block the implantation.